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LH1594/LH1595
LH1594/LH1595
DESCRIPTION
The LH1594/LH1595 are LCD drivers with a built-in character ROM suitable for driving small scale dotmatrix LCD panels, and which are capable of being directly connected to the bus line of a microcomputer. The 8-bit parallel or serial data transferred from a microcomputer is used to generate LCD drive signals for displaying characters. Incorporating a character ROM which has font characters configured in the format of 5 x 8 dots and a character RAM which allows the user to define characters, the LH1594/LH1595 provide a higher freedom of display. Since the LH1594/LH1595 have 80 output pins for a segment drive circuit and 17 output pins for a common drive circuit in a single chip, a display system for 16 characters x 2 lines can be implemented easily. The LH1594/LH1595 enable an LCD system for battery-operated, handcarrying information equipment by securing lower power consumption and wider operating voltage range.
80-Segment and 17-Common Outputs LCD Driver IC with A Built-in CGROM
* Abundant command functions - Display of 2 lines by 16 characters - Display ON/OFF - Normal/reverse display control - Busy flag readout - Cursor display - Blinking : per character - Display double fonts lengthwise - Power saving mode * LCD drive power circuit - Built-in booster circuit : Two or three times voltage boost is possible - Built-in voltage converter : Generates LCD drive voltages (V0, V1, V2, V3 and V4) based on the boosted voltage - Built-in power bias ratio : 1/4 or 1/5 bias (selectable by command) - Built-in electronic volume : Controllable in 16 steps - Supply voltages Logic system : +2.2 to +5.5 V LCD drive system : +4.0 to +11.0 V * Operating temperature : -30 to +85 C * Package : 151-pin TCP (Tape Carrier Package)
* Purchase of I2C components of Sharp Corporation, or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
FEATURES
* Built-in CGROM : 240 characters (5 x 8 x 240 = 9 600 bits) * Built-in CGRAM : 8 characters (5 x 8 x 8 = 320 bits) * Built-in SEGRAM : 80 segments (16 x 7 = 112 bits) * Built-in display data RAM : 32 characters (32 x 8 = 256 bits) * Format of font character : 5 x 8 dots including 1 dot which also serves to display a cursor * General 8-bit MPU interface : Possible to directly connect 80-family or 68-family MPU to bus line * Possible to make serial interface (I2C BUS* format is for LH1594) * Ratio of display duty cycle : 1/8, 1/9, 1/16 or 1/17 (selectable by command)
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH1594/LH1595
PIN CONNECTIONS
151-PIN TCP
COM7 1 COM6 COM5 COM2 COM1 COM0 COMI COMS SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 SEG0 SEG1 SEG2
TOP VIEW
SEG77 SEG78 SEG79 SEGS5 SEGS6 SEGS7 SEGS8 SEGS9 COMS COM8 COM9 COM10 COM13 COM14 COM15 COMI 110
151 VR2 VR1 VOUT CAP2+ CAP2- CAP1+ CAP1- VEE VDD D7/SDA D6/SCL D5/SA0 D4/ISEL D3 D2 D1 D0 M FLM LP OSCO OSCI CKS CK PMODE RDB WRB P/S M86 RS CSB RESB TEST SHL1 SHL0 VSS V4 V3 V2 V1 111 V0
NOTE :
Doesn't prescribe TCP outline.
2
CHIP SURFACE
LH1594/LH1595
BLOCK DIAGRAM
SEGS0 SEGS4 SEGS5 SEGS9 COM15 COMS COMS SEG79 COM0 COM7 COM8 COMI 9 COMI 110 117 SHL0 118 SHL1 111 V0 112 V1 113 V2 LCD POWER SUPPLY CIRCUIT 114 V3 115 V4 146 CAP1+ 145 CAP1- 148 CAP2+ 147 CAP2- 149 VOUT 150 VR1 151 VR2 127 PMODE OSC 144 VEE TIMING CONTROL CIRCUIT SEG0
15
11
96 100 10 101
16
95
8
1
102 109
RESB 120 CSB 121 RS 122 RDB 126 WRB 125 M86 123 P/S 124 D0 135 D1 136 D2 137 D3 138 D4/ISEL 139 D5/SA0 140 D6/SCL 141 D7/SDA 142 TEST 119 MPU INTERFACE
ANNUNCIATOR DRIVE CIRCUIT
LCD DRIVE CIRCUIT
ADDRESS COUNTER
DDRAM
LATCHING CIRCUIT
SHIFT REGISTER
INSTRUCTION DECODER CGRAM DATA HOLDER P/S CONVERSION CIRCUIT
BUSY
SEGRAM
CURSOR BLINKING CONTROL CIRCUIT
CGROM
OSCI 130 OSCO 131 CK 128 CKS 129
132 133 134 LP FLM M
143 116 VDD VSS
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LH1594/LH1595
1. PIN DESCRIPTION 1.1. Power Supply Pins
SYMBOL VDD VSS I/O DESCRIPTION Power supply Power supply pin for logic, connected to +2.2 to +5.5 V. Power supply Ground pin, connected to 0 V. Bias power supply pins for LCD drive voltage. * When using an external power supply, convert impedance by using resistancedivision of LCD drive power supply or operational amplifier before adding voltage to V0 V1 V2 V3 V4 the pins. * When using the external power supply, maintain the following power supply conditions. Power supply VSS < V4 < V3 < V2 < V1 < V0 * When the power supply circuit is ON, LCD drive voltage of V0 to V4 are generated by the internal booster circuit and voltage converter. * When using the internal power supply, be sure to connect each capacitor between V0 to V4 and VSS.
1.2. LCD Power Supply Circuit Pins
SYMBOL CAP1+ CAP1- CAP2+ CAP2- VEE VOUT VR1 VR2 PMODE I/O O O O O Power Supply DESCRIPTION Connecting pin for the internal booster's capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the internal booster's capacitor - side. The capacitor is connected between CAP1+ and CAP1-. Connecting pin for the internal booster's capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the internal booster's capacitor - side. The capacitor is connected between CAP2+ and CAP2-. Voltage supply pin for generating boosted voltage in the internal booster circuit. Usually the same voltage level as VDD.
Power Supply/ Output pin of boosted voltage in the internal booster circuit. O The capacitor must be connected between VSS and VOUT. I Used as input pins for voltage converter. Voltage must be input between the VEE and VOUT pins by voltage divided by resistors. Pin for controlling LCD power supply. I A combination of PMODE pin and ON/OFF command of power supply (PON) enables selection of a specific drive operation.
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LH1594/LH1595
1.3. System Bus Pins
SYMBOL I/O DESCRIPTION * When set to parallel interface mode (P/S = "H"). Used as an 8-bit bi-directional data bus (D7 to D0), which is connected to 8-bit MPU data bus. * When set to serial interface mode (P/S="L"). Used as serial interface signals (SDA, SCL, SA0, ISEL). [SDA] D0 D1 D2 D3 D4/ISEL D5/SA0 D6/SCL D7/SDA I/O LH1594 : I/O pin for the I2C BUS data line when serial interface is selected. Must be connected to a positive power supply via pull-up resistor. LH1595 : Serial-data input pin at time of serial interface selection. [SCL] LH1594 : Input pin for the I2C BUS clock signal when serial interface is selected. Must be connected to a positive power supply via pull-up resistor. LH1595 : Serial clock pin at time of serial interface selection. [SA0] LH1594 : Used for LSB bit of slave address for I2C BUS (7 bits width). Must be fixed to "H" or "L". LH1595 : Must be set to "L". If set to "H", LH1595 operation is not warranty. [ISEL] LH1594 : Used to identify I2C BUS. When using I2C BUS, fix to "H". If ISEL is set to "L", LH1594 operation is not warranty. CSB RS I I LH1595 : Must be set to "L". If set to "H", LH1595 operation is not warranty. Chip selection input pin that decoded address bus signal is input. Distinguishes display RAM data/commands of D7 to D0 data transferred from MPU. 1 : The data of D7 to D0 show the display RAM data. 0 : The data of D7 to D0 show the command data. Initialized by setting to "L". The reset signals of the system are normally input. Reset operation is performed in accordance with RESB signal level. * In connecting to 80-family MPU : This RDB is a pin for connecting the RDB signal of 80-family MPU. When the RDB (E) signal enters in the "L" state, the data bus of this IC turns to the "output" state. I * In connecting to 68-family MPU : This RDB becomes a pin for connecting the enable clock signal of 68-family MPU. When the signal enters in the "H" state, the data bus of this IC turns to the "active" state.
RESB
I
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LH1594/LH1595
SYMBOL I/O * In connecting to 80-family MPU : This WRB is a pin for connecting the WRB signal of 80-family MPU, and when WRB signal is "L", this pin is "active". The data bus signal is input at the rising edge of WRB signal. I * In connecting to 68-family MPU : This WRB becomes a pin for connecting the R/W signal of controlling read/write of 68-family MPU. R/W = "H" : Read R/W = "L" : Write MPU interface-type shift pin. M86 = "H" : 68-family interface M86 = "L" : 80-family interface Fixed to either "H" or "L". Used to shift between parallel interface and serial interface. P/S I P/S = "H" for parallel interface. Fix SDA and SCL pins to either "H" or "L". P/S = "L" for serial interface. Fix D3 to D0 pins to High-Z, RDB and WRB pins to either "H" or "L". For testing. Fix to "L". DESCRIPTION
WRB (R/W)
M86
I
TEST
I
1.4. LCD Drive Circuit Signals
SYMBOL LP I/O O DESCRIPTION The latching signal of display data to count up the display line counter at the rising, and to output the LCD drive signals at the falling. Output pin for LCD display synchronous signals (first line marker). FLM M O O When FLM pin is set to "H", the display starting line address is preset in the display line counter. Output pin for alternating signals of LCD drive output. Segment output pins for LCD drive. According to the data of the display data, non-lighted at "0", lighted at "1" (Normal mode) non-lighted at "1", lighted at "0" (Reverse mode) and, by a combination of M signal and display data, one signal level among V0, V2, V3, and VSS is selected. SEG0-SEG79 O
M Signal
Display Data
Normal Mode Reverse Mode
V2 V0
V0 V2
V3 VSS
VSS V3
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LH1594/LH1595
SYMBOL I/O DESCRIPTION Common output pins for LCD drive. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS is selected. Output level M Data VSS H H L H L H L L V1 V0 V4
COM0-COM15
O
Common output pin for marker display. When executing duty + 1 (PLUS) command, it functions as a common output pin. Having two output pins for COMI, they output same level. It is able to select output COMI O pin for COMI when wiring pattern. Duty + 1 ON Duty + 1 OFF COM16 (when displaying 2 lines), COMI state V0 or V4 COM8 (when displaying 1 line) Common drive output pin for static LCD drive (for annunciator display). Having two output pins for COMS, they output same level. It is able to select output pin for COMS when wiring pattern. When DA = "0", outputs VSS level. Segment drive output pin for static LCD drive (for annunciator display). SEGS0-SEGS9 O One level is selected from VDD and VSS levels depending on the combination of COMS signal and display data. When DA = "0", outputs VSS level. Input pin to control the transfer direction of the segment and common signal output data. SHL0 SHL1 I SHL0 = "0" : Segment data display direction is SEG0 to SEG79. SHL0 = "1" : Segment data display direction is SEG79 to SEG0. SHL1 = "0" : Common data display direction is COM0 to COM15. SHL1 = "1" : Common data display direction is COM15 to COM0.
COMS
O
1.5. Pins for Oscillation Circuit
SYMBOL OSCI OSCO I/O I O DESCRIPTION Feedback-resistance connecting pin for the internal oscillation circuit. Input pin of display master clock. CK I When using CK pin as an input of the master clock, fix OSCI pin to VSS. When using the internal oscillation circuit as the display master clock, fix CK pin to VSS. Selection input pin of display master clock. CKS I CKS = "H" : Input the external clock to CK pin. CKS = "L" : The internal oscillation circuit by using OSCI and OSCO pins is used.
* Master clock : Clock for oscillation circuit or external clock.
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LH1594/LH1595
1.6. Input/Output Circuits
VDD
I
To Internal Circuit
VSS (0 V)
Applicable pins M86, P/S, SHL0, SHL1, OSCI, CK, CKS, PMODE, RESB, TEST
Fig. 1 Input Circuit (1)
VDD
I
To Internal Circuit
VSS (0 V) Input Control Signal
VSS (0 V)
Applicable pins CSB, RS, WRB, RDB
Fig. 2 Input Circuit (2)
VDD
I
O
To Internal Circuit
VSS (0 V) VDD
Output Control Signal
Output Signal VSS (0 V)
Applicable pin OSCO
Fig. 3 Input/Output Circuit (1)
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LH1594/LH1595
VDD
I
O
To Internal Circuit
VSS (0 V)
VSS (0 V)
Input Control Signal VDD
Output Control Signal
Output Signal VSS (0 V)
Applicable pins D7-D0
Fig. 4 Input/Output Circuit (2)
VDD
VDD
O
Output Signal
VSS (0 V)
VSS (0 V)
Applicable pins LP, FLM, M, SEGS0-SEGS9, COMS
Fig. 5 Output Circuit
V0 V0 Output Control Signal 1
V1/V2 Output Control Signal 2
O
Applicable pins
Output Control Signal 3 VSS (0 V) V3/V4 VSS (0 V) VSS (0 V) Output SEG0-SEG79, Control Signal 4
COM0-COM15, COMI
Fig. 6 LCD Drive Output Circuit
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LH1594/LH1595
2. FUNCTIONAL DESCRIPTION 2.1. MPU Interface
2.1.1. INTERFACE TYPE SELECTION The LH1594/LH1595 transfer data through 8-bit parallel I/O (D7 to D0) or serial data input (SDA, SCL).
P/S H L I/F TYPE Parallel Serial CSB RS CSB RS - (LH1594) - (LH1594) CSB (LH1595) RS (LH1595) RDB RDB -
The selection between parallel interface and serial interface is made by setting the state of P/S pin to "H" or "L".
WRB WRB - M86 M86 - SDA - SDA SCL - SCL DATA BUS D7 to D0 -
2.1.2. PARALLEL INPUT The LH1594/LH1595 can transfer data in parallel by directly connecting 8-bit MPU to the data bus when parallel interface is selected with P/S pin.
M86 H L MPU TYPE 68-family MPU 80-family MPU CSB CSB CSB RS RS RS
As an 8-bit MPU, either 80-family MPU interface or 68-family MPU interface is selected with M86 pin.
RDB E RDB
WRB R/W WRB
DATA D7 to D0 D7 to D0
2.1.3. DATA IDENTIFICATION The LH1594/LH1595 can identify the data of 8-bit data bus by combinations of RS, RDB and WRB signals.
68-FAMILY R/W 1 0 1 0 80-FAMILY RDB WRB 0 1 1 0 1 0 1 0
RS 0 0 1 1
FUNCTION Reads out busy flags Writes to commands Reads from data RAM Writes to data RAM
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LH1594/LH1595
2.1.4. SERIAL INTERFACE [FOR LH1594] The serial interface for the LH1594 is I2C BUS format. I2C BUS is for bi-directional two-line communication between different ICs or other modules. LH1594 always operates as a slave device, so sending data of start and stop is controlled by start/stop bits which are sent by master device. [FOR LH1595] The serial interface of LH1595 can accept inputs of SDA and SCL in the chip selection state (CSB = "L"). When not in the chip selection state, the internal shift register and counter are reset to their initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising edge of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data.
The identification whether the serial data inputs (SDA) are display data or commands is judged by input to RS pin. RS = "H" : Display data RS = "L" : Commands After completing 8-bit data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Protection of SDA and SCL signals against external noise should be taken in actual wiring. To prevent the successive recognition errors of transferring data from external noise, release the chip selection state (CSB = "H") at every completion of 8-bit data transferring.
CSB
RS
Valid
SDA
D7
D6
D5
D4
D3
D2
D1
D0
SCL 1 2 3 4 5 6 7 8
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LH1594/LH1595
2.2. Busy Flag
When the busy flag is "1", this indicates that the LH1594/LH1595 are internally operating. In this state, the LH1594/LH1595 do not accept the next instruction. As shown in the command function table, the busy flag is output to the data bus D7 when RS is "0" or R/W is "1" (for the 68-family interface), and when RS is "0" or RDB is "0" (for the 80-family interface). The busy flag is generated only when the display clear command or the ACL command is executed. It must be confirmed that the busy flag is "0" before the next instruction can be executed.
2.7. Segment RAM (SEGRAM)
The SEGRAM allows user-written programs to freely control icons and marks. When the COMI outputs the selection signal, the data stored in the SEGRAM is read out to display 80 segments.
2.8. Timing Generation Circuit
The timing generation circuit generates the timing signals to operate the internal circuits, including the DDRAM, CGROM, CGRAM, and SEGRAM, as well as those for segment and common drive outputs. Readout of the display data to the LCD drive circuit is completely independent of MPU. Therefore, a MPU that has no relationship the readout operation of the display data can access it.
2.3. Address Counter (AC)
The address counter (AC) is used to address the DDRAM, CGRAM, or SEGRAM. When the addressing instruction is written into the AC, the address information is transferred to the AC. Simultaneously, the instruction also determines which RAM is to be selected among the DDRAM, CGRAM, and SEGRAM. After data is written into (read out from) the DDRAM, CGRAM, or SEGRAM, the AC is automatically counted up or down by one. As shown in the command function table, the AC outputs data to the data buses D6 to D0 when RS is "0" and R/W is "1" (for the 68-family interface).
2.9. Cursor Blinking Control Circuit
This circuit generates the cursor, the blinking cursor, or the reverse-display cursor. The cursor or the blinking cursor appears in the digit that corresponds to the address in the DDRAM which is specified in the address counter.
2.4. Display Data RAM (DDRAM)
The DDRAM stores display data presented with 8bit character codes. Its capacity is 32 characters in a format of 8 bits.
2.5. Character Generator ROM (CGROM)
The CGROM generates 240 different character patterns in a format of 5 x 8 dots from 8-bit character codes.
2.6. Character Generator RAM (CGRAM)
The CGRAM allows user-written programs to freely overwrite characters. Eight different types of characters can be written in a format of 5 x 8 dots.
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LH1594/LH1595
2.10. Output Timing of LCD Driver
Display timing at normal mode, 1/16 duty
15 LP FLM M
16
1
2
3
16
1
2
3
16
1
V0 V1 COM0
V4 VSS
V4 VSS
V0 V1 COM1 V1 V1
V4 VSS
V4
V4
V0 SEG0 V2 V3 VSS V3
V0
V0 V2 SEG1 V3 V2 V3 VSS V3 V2
SEG0 COM0 COM1
SEG1
SEG2
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LH1594/LH1595
2.11. LCD Drive Circuit
This drive circuit generates 4 levels of LCD drive voltage. The circuit has 80 segment outputs and 17 common outputs and outputs combined display data and M signal. Character data is transferred by 80 bits from the CGROM or the CGRAM to the segment drive circuit. One of the common outputs, COMI is for marker display only. A common drive circuit that has a shift register sequentially outputs common scan signals.
2.12. Oscillation Circuit
The frequency of this CR oscillator is controlled by the feedback resistor RF. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster circuit. If external clock is used, maintain OSCI pin at VSS and OSCO pin open (NC), and feed the clock to CK pin. The duty cycle of the external clock must be 50%. The CKS pin is used to select either internal oscillation circuit or external clock.
CKS OSCILLATION CIRCUIT L Enabled H Disabled EXTERNAL CLOCK Disabled Enabled
the voltage converter which converts this high input voltage into V0, V1, V2, V3 and V4 which are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels or a large LCD panel that has large capacity consisting of more than one chip. Otherwise, display quality will degrade considerably. Instead, use an external power supply. This internal power supply is controlled by the power supply circuit ON/OFF command (PON). When the internal power supply is turned off, the booster circuit and voltage converter are also turned off. When using the external power supply, turn off the internal power supply, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, VOUT, VEE, VR1 and VR2, and keep PMODE pin at VSS. Then, feed external LCD drive voltages to pins V0, V1, V2, V3 and V4. This circuit can be changed by the state of PMODE pin.
PON PMODE 0 0 1 1 0 1 0 1 BOOSTER VOLTAGE EXTERNAL NOTE 1 1 2
CIRCUIT CONVERTER VOLTAGE INPUT Disabled Disabled V0, V1, V2, V3, V4 Disabled Disabled V0, V1, V2, V3, V4 Enabled Disabled Enabled Enabled - VOUT, VR1, VR2
2.13. Annunciator Circuit
This is the drive circuit which generates 2-value levels for static LCD drive. This circuit provides displaying annunciators for icons or marks. It consists of common drivers (COMS x 2) and 10 segment drivers (SEGS0 to SEGS9). One level is selected from VDD and VSS levels for static LCD drive. When this circuit is not displaying annunciator, it outputs VSS level.
NOTES :
1. Because the booster circuit and voltage converter are not functioning, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, VOUT, VEE, VR1, and VR2. Apply external LCD drive voltages to corresponding pin. 2. Because the booster circuit is not functioning, disconnect pins CAP1+, CAP1-, CAP2+, CAP2- and VEE. Derive the voltage source to be supplied to the voltage converter from VOUT pin and then output LCD drive voltage to VR1, and VR2 pins. The voltage level at VR1 and VR2 pins must be VR2 VR1 VOUT.
2.14. Power Supply Circuit
This circuit supplies voltages necessary to drive an LCD. The circuit consists of booster circuit and voltage converter. Boosted voltage from the booster circuit is fed to
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LH1594/LH1595
2.15. Booster Circuit
Placing capacitor C1 across CAP1+ and CAP1- and across CAP2+ and CAP2- and across VOUT and VSS boosts the voltage coming from VEE and VSS three times and outputs the boosted voltage to VOUT pin. Placing C1 across CAP1+ and CAP1- and shorting together pins CAP1+ and CAP2+ limits the output on VOUT pin to two times the input voltage. Since the booster circuit uses the clock derived from the internal oscillation circuit or external clock as the boosting clock, the internal oscillation circuit must be enabled, or if external clock is selected, it must be fed to CK pin. The output level at the VOUT pin does not exceed the recommended maximum operating voltage (11.0 V) when the voltage is boosted. If this value is exceeded, the operation of the LH1594/LH1595 are not covered by warranty.
VOUT = 9 V
VOUT = 6 V
VEE = 3 V
VEE = 3 V
VSS = 0 V When Boosted Two Times
VSS = 0 V When Boosted Three Times
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LH1594/LH1595
2.16. Voltage Control Circuit
The boosted voltage at the VOUT pin is connected to the VR1 and VR2 pins and then the LCD drive voltages (V0, V1, V2, V3, and V4) are generated via the voltage converter circuit. The input level at the VR1 and VR2 must meet the electric potential condition of VR1 VR2. The internal electronic volume divides the electric potential between the VR1 and VR2 into 16 segments. Since the VR1 and VR2 pins have high input impedance, the input voltage levels at the VR1 and VR2 are determined by the resistance ratio of R1, R2, and R3. The current flowing between the VOUT and VSS pins is determined by the combined resistance of R1, R2, and R3. Therefore, R1, R2, and R3 must be selected in accordance with the above current as well as the input voltage levels at the VR1 and VR2. The boosted voltage at the VOUT pin originates from the voltage supplied at the VEE pin. Thus, the DC path current generated with R1, R2, and R3 connected between the VOUT and VSS pins is supplied as current at the VEE pin. The electric current value, three times larger than the DC path current generated between the VOUT and VSS pins when the voltage is tripled, is added as supply current at the VEE pin (two times larger current is added for doubled voltage). Take sufficient care that the input levels at the VR1 and VR2 pins do not fluctuate with external noise (connect capacitor C3).
2.17. Electronic Volume
The voltage converter incorporates an electronic volume, which allows the LCD drive voltage level V0 to be controlled with a command and also allows the tone of LCD to be controlled. If 4-bit data is stored in the register of the electronic volume, one level can be selected among 16 voltage values for the LCD drive voltage V0. The voltage control range of the electronic volume is determined by the input voltage levels at the VR1 and VR2. This means that the voltage range of (VR1 to VR2) is the controllable voltage range of the electronic volume. The electric potential relation between the VR1 and VR2 pins must be VR1 VR2. The input voltage levels at the VR1 and VR2 pins must be selected in accordance with the voltage levels to be obtained with the electronic volume.
2.18. LCD Drive Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, that is, V1, V2, V3 and V4, are obtained by dividing V0 through a resistor network. The LCD drive voltages from LH1594/LH1595 are biased at 1/4 or 1/5. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. In this case, connect a capacitor C3 to stabilize input voltage to VR1 and VR2. A value of C3 can be defined selectively.
C1 R1 C3 R2 C3 R3
VOUT LH1594/LH1595 VR1
VR2
VSS
Example of Voltage Control Circuit
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LH1594/LH1595
2.19. Example of Power Supply Circuit
VDD VDD VEE CAP1+ C1 CAP1- CAP2+ C1 CAP2- VOUT VR1 VR2 VSS V0 V1 V0 C2 V1 C2 V2 V3 V4 V2 C2 V3 C2 V4 C2 OSCI RF OSCO CKS When Using The External Power Supply VSS RF OSCO CKS When Using The Internal Power Supply OSCI V4 V3 V2 V1 CAP2- VOUT R1 VR1 R2 VR2 R3 VSS VSS V0 CAP1- CAP2+ VDD VDD VEE CAP1+
C1 VSS C3 VSS C3 VSS
External Power Supply
Recommended values
C1 C2 C3 RF R1 + R2 + R3 1.0 to 5.0 F (B)* 0.1 to 5.0 F (B)* 0.01 to 0.1 F 1.2 M$ 2.0 to 4.0 M$
* B characteristics must be used with C1 and C2.
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LH1594/LH1595
2.20. Initialization
The LH1594/LH1595 are initialized by setting RESB pin to "L". Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power is ON, be sure to reset operation.
PARAMETER Function PIN DESCRIPTION RE = 0 : Writes to expanded register disabled. BE = 0 : SEGRAM blink OFF DUB = 0 : Normal display mode (Displaying double fonts lengthwise OFF) BT = 0 : Blinking type is normal/ reverse display. Entry mode Display mode Display control (1) I/D = 1 : Increments by one. S = 0 : No shift occurs. NL = 0 : Displays 2 lines. D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF Display control (2) PLUS = 0 : 1/16 duty REV = 0 : Normal display ALON = 0 : Normal display Power control HALT = 0 : Power saving OFF PON = 0 : Power supply circuit OFF ACL = 0 : ACL operation OFF BIAS : 1/5 bias Register in electronic volume Annunciator control (1, 1, 1, 1) DA = 0 : Annunciator display OFF I0 to I9 = (0, 0, 0, 0, 0, 0, 0, 0, 0, 0) RAM data DDRAM : Not determined. CGRAM : Not determined. SEGRAM : Not determined.
3. PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows. q When using an external power supply o When connecting the power supply After connecting the logic system power supply, make reset operation and then apply external LCD drive voltages to corresponding pins. (V0, V1, V2, V3, V4 or VOUT, VR1 and VR2) o When disconnecting the power supply After executing HALT command, disconnect external LCD drive voltages and then disconnect the logic system power supply. w When using the internal power supply o When connecting the power supply After connecting the logic system power supply, make reset operation and then execute PON command. o When disconnecting the power supply After executing HALT command, disconnect the logic system power supply. It is advisable to connect the serial resistor (50 to 100 $) or fuse to the LCD drive power VOUT or V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade.
18
LH1594/LH1595
4. COMMAND FUNCTION
Since the instructions for the LH1594/LH1595 are executed within execution cycle time, the MPU can be operated at a high speed without a waiting time. The busy state check is only necessary when the display clear command or the ACL command is executed.
4.1. Command Function Table
INSTRUCTION RAM data write RAM data read Display clear set Cursor home set Entry mode set Display mode set Display control (1) set RE 0/1 0/1 0/1 0/1 0 1 0 0 Display control (2) set Cursor/display shift set 1 0 0 0 0 1 D RS 1 1 0 0 0 0 0 0 0 0 D7 INSTRUCTION CODE D6 D5 D4 D3 D2 WRITE DATA READ DATA 0 0 0 0 0 0 0 1 I/D * C 1 * S NL B D1 D0 DESCRIPTION Writes to data RAM. Reads from data RAM. Specifies address 0 from DDRAM in AC after clearing all display. Allocates address 0 for DDRAM in AC and resets shifted display. Specifies cursor moving direction and whether or not to shift display. Sets display 2 lines or 1line (NL). Turns ON/OFF all display (D). Turns ON/OFF cursor (C). Specifies blinking character indicated by cursor (B). Specifies duty + 1 (PLUS). PLUS REV ALON Displays data in reverse display (REV). Turns ON all display (ALON). Moves cursor and shifts display without changing data in DDRAM. Specifies HALT ON (HALT). BIAS HALT PON ACL Turns ON power supply circuit (PON). Specifies resetting (ACL). Sets bias ratio (BIAS). Enables writes to expanded register (RE). Enables blinking for SEGRAM (BE). Enables display double font lengthwise (DUB). Sets blinking character type (BT). Sets CGRAM address. Sets SEGRAM address. Sets DDRAM address. Sets electronic volume. I0 I6 Sets data for annunciator (I0 to I9). Enables display annunciator (DA). Reads out busy flag and data from AC.
0
0
0
0
0
0
1
0 0 0 0 0 1
S/C
R/L
*
*
Power control set
1
Function set
0/1
0
0
0
1
BE DUB RE
BT
*
CGRAM address set SEGRAM address set DDRAM address set Electronic volume set Annunciator control set Busy flag/address read
0 1 0 1 0 1 0/1
0 0 0 0
0 1 1 BF
1 0 1 *
ACG * * * I5 DA * * I4 * I3 I9 AC ASEG ADD DVOL I2 I8 I1 I7
* mark means "Don't care".
19
LH1594/LH1595
4.2. Write Data to RAM
RE 0/1 RS 1 D7 D D6 D D5 D D4 D D3 D D2 D D1 D D0 D
Writes binary 8-bit data D7 to D0 to the CGRAM or DDRAM or SEGRAM. The RAM is to be written into is determined by the previous specification of CGRAM or DDRAM or
SEGRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode.
4.3. Read Data to RAM
RE 0/1 RS 1 D7 D D6 D D5 D D4 D D3 D D2 D D1 D D0 D
Reads binary 8-bit data D7 to D0 from the CGRAM or DDRAM or SEGRAM. The most recent set address command determines the RAM is to be read. After writing, the address
automatically increments or decrements by 1, in accordance with the entry mode.
4.4. Display Clear Register Set
RE 0/1 RS 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
Space code "20H" (for 32 characters) is written to all addresses in the DDRAM. The address counter specifies DDRAM address 0. If the display is shifted, it is reset in place. This means that the display is cleared and the cursor or blinking cursor, if displayed, returns to the left end in the first line. Set the I/D of the increment mode to "Increment". "S" will not change.
When the clearing of the display starts, the busy flag is generated. Therefore, to execute an instruction after clearing the display, monitor the busy flag and then execute the next instruction after checking that the flag has been released; or allow a waiting period of 34 times the master clock frequency.
4.5. Cursor Home Register Set
RE 0/1 RS 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 *
* mark means "Don't care". Specify DDRAM address 0 in the address counter. If the display is shifted, it is reset in place. The data in the DDRAM remains unchanged. The cursor or the blinking cursor, if displayed, returns to the left end in the first line.
20
LH1594/LH1595
4.6. Entry Mode Register Set
RE 0 RS 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 I/D D0 S
When the extended register enable bit (RE) is "0", the following I/D, and S bits are accessed : I/D : When any character code is written into or read out from the DDRAM, the DDRAM address is shifted by +1 (I/D = 1) or -1 (I/D = 0). In case of +1, the cursor or the blinking cursor moves to the right. This is also applicable when any data is written into or read out from the CGRAM or SEGRAM. : If S = 1, the entire display is shifted to either the left or right when any character code is written into the DDRAM. If I/D = 1, the entire display is
S
shifted to the left; or if I/D = 0, the entire display is shifted to the right. Therefore, if I/D = 1, the cursor looks stationary with only the display shifted. When any character code is read out from the DDRAM, the display is not shifted. If S = 0, the display remains unshifted. When any data is written into or read out from the CGRAM or SEGRAM, the display also remains unshifted. When duty + 1 command is ON (PLUS = 1), if S = 1 and any code is written into DDRAM, the line that COMI scans is also shifted, so that this command is allowed only when duty + 1 command is OFF (PLUS = 0) state.
4.7. Display Mode Register Set
RE 1 RS 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 * D0 NL
* mark means "Don't care". When the extended register enable bit (RE) is "1", the following NL bit is accessed : NL : This command selects the displaying lines. NL = "0" : Displays 2 lines. Display duty ratio is 1/16. NL = "1" : Displays 1 line. Display duty ratio is 1/8.
21
LH1594/LH1595
4.8. Display Control (1) Register Set
RE 0 RS 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 D D1 C D0 B
When the extended register enable bit (RE) is "0", the following D, C, and B bits are accessed : D : Turns ON the display if D = 1; or turns OFF the display if D = 0. Since the data in the DDRAM is retained, the display can be resumed by specifying D = 1. : Displays the cursor if C = 1; or hides the cursor if C = 0. Even if the cursor is hidden, I/D and other features remain
unchanged when the display data is written. The cursor is shown with 5 dots in the 8th line. B : Blinks the character in the cursor position if B = 1. This blinking turns ON/OFF all dots displayed in reverse. The blinking frequency is 300 ms when fOSC = 55 kHz and displays 2 lines. This value varies in proportion to the inverse number of fOSC.
C
4.9. Display Control (2) Register Set
RE 1 RS 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 PLUS D1 REV D0 ALON
When the extended register enable bit (RE) is "1", the PLUS, REV, and ALON bits are accessed. Once the specified values are stored in this register, they are retained even if the RE bit is set to "0". PLUS : Specifies "duty + 1". Toggles the display duty. The COMI pin functions as the COM8 (when displaying 1 line) or COM16 (when displaying 2 lines) for marker. When the COMI is scanned, the data in the SEGRAM is output as display data from the segment driver. PLUS = "0" : Sets the display duty to 1/8 (when displaying 1 line) or 1/16 (when displaying 2 lines). PLUS = "1" : Sets the display duty to 1/9 (when displaying 1 line) or 1/17 (when displaying 2 lines).
REV
: Toggles between normal and reverse videos for display. REV = "0" : Normal video REV = "1" : Reverse video
ALON : Toggles between normal and fully lit-up displays regardless the data type in the DDRAM. The setting of this bit takes priority over that of REV. ALON = "0" : Normal display ALON = "1" : Fully lit-up display
22
LH1594/LH1595
4.10. Cursor/Display Shift Register Set
RE 0 RS 0 D7 0 D6 0 D5 0 D4 1 D3 S/C D2 R/L D1 * D0 *
* mark means "Don't care". When the extended register enable bit (RE) is "0", the following S/C and R/L bits may be set. The cursor position or the display is shifted to the left or right without writing the display data or reading it out. This may be used to modify or search the display. The cursor movement from the 1st to 2nd line occurs after the 16th digit in the 1st
S/C 0 0 1 1 R/L 0 1 0 1
line. Note that all the lines are shifted simultaneously. When duty + 1 command is ON (PLUS = 1), if S = 1 and any code is written into DDRAM, the line that COMI scans is also shifted, so that this command is allowed only when duty + 1 command is OFF (PLUS = 0) state.
ACTION Shifts cursor to left (counts down the AC by one). Shifts cursor to right (counts up the AC by one). Shifts entire display to left. Cursor moves as display is shifted. Shifts entire display to right. Cursor moves as display is shifted.
If only the display shift is made, the address counter (AC) remains unchanged.
4.11. Power Control Register Set
RE 1 RS 0 D7 0 D6 0 D5 0 D4 1 D3 D2 D1 PON D0 ACL BIAS HALT
BIAS : This command selects the displaying bias ratio. BIAS = "0" : 1/5 bias BIAS = "1" : 1/4 bias HALT : Turns ON/OFF the power saving mode. When the LH1594/LH1595 enter the power saving mode, the supply current can be reduced to nearly the standby current value. HALT = "0" : Normal mode HALT = "1" : Power saving mode The internal state in the power saving mode is described below. * The oscillation and power circuits are stopped.
* The LCD drive is disabled. The output from the segment and common drivers are made at the VSS level. * The clock input at the CK pin is inhibited. PON : Turns ON/OFF the internal power supply circuit. PON = "0" : Turns OFF the power supply circuit. PON = "1" : Turns ON the power supply circuit. The booster circuit and the voltage converter become active when the power supply circuit is turned on. The operating section in the circuits varies depending on the setting of the PMODE pin. See Table in Section 2.14. for details.
23
LH1594/LH1595
ACL : The internal circuit can be initialized. ACL = "0" : Normal mode. ACL = "1" : ACL operation is ON. When the ACL command is turned on, the busy flag is generated. Therefore, to execute an instruction after ACL operation, monitor the busy flag and then execute the next instruction after checking that the flag has been released; or allow a waiting period of 2 times the master clock frequency.
4.12. Function Register Set
RE 0/1 RS 0 D7 0 D6 0 D5 1 D4 BE D3 DUB D2 RE D1 BT D0 *
* mark means "Don't care". RE : This bit is the enable bit for extended register. If RE = "1", the extended function setting can be accessed. When setting instruction, it is necessary to follow the state of RE bit. (refer to "INSTRUCTION CODE" in section 4.1..) RE bit consists of register, once the specified value is stored in this register, it is retained the value. : When BE = "1", the information which is stored in the SEGRAM using its upper 2 bits is used to allow for blinking the display data from the SEGRAM. DUB : This bit is toggled the display double fonts lengthwise. DUB = "0" : Displays normal mode. DUB = "1" : Displays double fonts lengthwise. NOTES :
* Double fonts lengthwise can display only first line. * Not using these setting, when displaying 1 line mode. (NL = 1)
BE
Example of Display (DUB = "1")
BT
: This command selects the character blinking type. BT = "0" : Displaying normal/reverse per 32 frames.
BT = "1" : Displaying normal/black per 32 frames.
Example of Display (BT = "0")
Example of Display (BT = "1")
24
LH1594/LH1595
4.13. CGRAM Address Register Set
RE 0 RS 0 D7 0 D6 1 D5 A D4 A D3 A D2 A D1 A D0 A
If the extended register enable bit (RE) is "0", CGRAM addresses may be specified. In the above example, the address shown in binary
number for "AAAAAA" is allocated in the address counter. Subsequently data is written into or read from the MPU in reference to the CGRAM.
4.14. SEGRAM Address Register Set
RE 1 RS 0 D7 0 D6 1 D5 * D4 * D3 A D2 A D1 A D0 A
* mark means "Don't care". If the extended register enable bit (RE) is "1", SEGRAM addresses may be specified. The SEGRAM address shown in binary number for "AAAA" is allocated in the address counter. Subsequently data is written into or read from the MPU in reference to the SEGRAM.
4.15. DDRAM Address Register Set
RE 0 RS 0 D7 1 D6 0 D5 * D4 A D3 A D2 A D1 A D0 A
* mark means "Don't care". If the extended register enable bit (RE) is "0", DDRAM addresses may be specified. The DDRAM address shown in binary number for "AAAAA" is allocated in the address counter. Subsequently data is written into or read from the MPU in reference to the DDRAM.
4.16. Electronic Volume Register Set
RE 1 RS 0 D7 1 D6 0 D5 * D4 * D3 MSB D2 D1 D0 LSB
* mark means "Don't care". The LCD drive voltage V0 output from the internal power supply circuit can be controlled and the display tone on the LCD can be also controlled. The LCD drive voltage V0 takes one out of 16 voltage values by setting 4-bit data register. If the electronic volume is not used, specify (1, 1, 1, 1) in the 4-bit data register. After the LH1594/LH1595 are reset, the 4-bit data register is automatically set to (1, 1, 1, 1).
MSB 0 0 0 | 1 1 1 1 LSB 0 V0 Smaller | Larger
25
LH1594/LH1595
4.17. Annunciator Control Register Set
RE 0 1 RS 0 D7 1 D6 1 D5 I5 DA D4 I4 * D3 I3 I9 D2 I2 I8 D1 I1 I7 D0 I0 I6
* mark means "Don't care". I0 to I9 : These bits are setting data for annunciator. Io to I9 correspond to SEGS0 to SEGS9 for static LCD drive outputs. DA : When DA = "1", output pin for static LCD drive (for annunciator display). One level is selected from VDD and VSS levels depending on the combination of COMS signal and display data (I0 to I9). When DA = "0", outputs VSS level.
Display OFF ("DA" = "0")
Display ON ("DA" = "1")
"VDD" COMS "VSS" "VSS"
"VDD" SEGS0 "VSS" "VSS" Not lighted
"VDD" SEGS1 "VSS" "VSS"
Lighted
1 Frame
1 Frame
Example of Outputs for Annunciator (DA = "1", I0 = "0", I1 = "1")
4.18. Busy Flag/Address Read
RE 0/1 RS 0 D7 BF D6 * D5 A D4 A D3 A D2 A D1 A D0 A
* mark means "Don't care". "BF = 1" indicates that the LH1594/LH1595 are internally operating and the next instruction is not accepted until "BF = 0". The busy flag is only generated when the display is cleared or the ACL command is executed. Therefore, any other instruction can be executed without monitoring the busy flag. Simultaneously, the address counter value presented in binary number for "AAAAAA" is read out. The address counter is used by the DDRAM, CGRAM, and SEGRAM. The data read out from the RAMs is determined by specifying a command before reading out.
26
LH1594/LH1595
4.19. Example of Instructions vs. Display
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cursor home 0000 INSTRUCTION RS D7 D6 D5 D4 D3 D2 D1 D0 Power ON Function set 000 DISPLAY ACTION No display appears. "0" is written to RE bit. Display is cleared. _ _ S_ Turns ON display and cursor. If display is cleared, display is filled with blank spaces. Counts up address by one and moves cursor to right when data is written to RAM. Writes "S".
1
* 0 0
* 0 1 0 0
0 0 1 1 0
0 0 1 1 1
* 1 0 0 1
Display clear 0000 0000 Entry mode set
Display ON/OFF control
00000 DDRAM data write 1 0 1 0 1 : : DDRAM data write 10101 DDRAM address set 010*1 DDRAM data write 1 0 1 0 0 : : DDRAM data write 10101 : : 0
0 0 1
0 0 1
0 0 0
0 0 0
SHARP_ SHARP _ SHARP L_
Writes "P". Sets DDRAM address so that cursor is positioned at the top of 2nd line. Writes "L".
0
0
1
0
SHARP LCDDRIVER_
Writes "R".
0
0
1
*
SHARP _ LCDDRIVER
Resets both display and cursor in place (address 0).
* mark means "Don't care".
27
LH1594/LH1595
5. CONFIGURATION OF CGROM
Character codes vs. character patterns
Low order High order
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
XXXX0000
CG RAM (1) CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8) CG RAM (1) CG RAM (2) CG RAM (3) CG RAM (4) CG RAM (5) CG RAM (6) CG RAM (7) CG RAM (8)
XXXX0001
XXXX0010
XXXX0011
XXXX0100
XXXX0101
XXXX0110
XXXX0111
XXXX1000
XXXX1001
XXXX1010
XXXX1011
XXXX1100
XXXX1101
XXXX1110
XXXX1111
28
LH1594/LH1595
6. CONFIGURATION OF CGRAM
CGRAM addresses vs. character codes (DDRAM) and character patterns (CGRAM).
CHARACTER CODE CGRAM ADDRESS CGRAM DATA D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0000*000000000***10001 10001 001 10001 010 01010 011 1 1 1 1 : 0 0 0 0 * 1 1 1 1 : 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * 0 0 1 1 0 1 0 1 : * * 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 (H) 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 (Y)
* mark means "Don't care".
Upper section : Character pattern 1 (Y display) Lower section : Character pattern 2 (H display)
NOTES:
1. Character code bits D2 to D0 correspond to CGRAM addresses A5 to A3 (3 bits : 8 types). 2. CGRAM addresses A2 to A0 correspond to line positions of the character pattern (3 bits : 8 lines). 3. The columns of the character pattern are laid out with bit 0 allocated to the right end. Therefore, the pattern of bits 4 to 0 is displayed. 4. If the upper 4 bits (D7 to D4) of the character code are zeros, the CGRAM is selected. Since bit D3 is "Don't care", "00H" and "08H" are the same CGRAM address. 5. If the CGRAM data is "1", data is displayed; if "0", data isn't displayed.
29
LH1594/LH1595
7. CONFIGURATION OF SEGRAM
SEGRAM addresses vs. display patterns
SEGRAM ADDRESS A2 A1 A0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 D6 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 SEGRAM DATA D5 D4 D3 D2 * * * * * * * * * * * * * * * * S0 S5 S10 S15 S20 S25 S30 S35 S40 S45 S50 S55 S60 S65 S70 S75 S1 S6 S11 S16 S21 S26 S31 S36 S41 S46 S51 S56 S61 S66 S71 S76 S2 S7 S12 S17 S22 S27 S32 S37 S42 S47 S52 S57 S62 S67 S72 S77 D1 S3 S8 S13 S18 S23 S28 S33 S38 S43 S48 S53 S58 S63 S68 S73 S78 D0 S4 S9 S14 S19 S24 S29 S34 S39 S44 S49 S54 S59 S64 S69 S74 S79
* mark means "Don't care". D7 and D6 : Blink control D4 to D0 : Pattern displayed NOTES :
1. Data stored in the SEGRAM is output for one-line display when COMI is selected. 2. Pins S0 to S79 are segment drive pins. Pin S0 is shown at the left end on the screen. 3. After output at pin S79, output at pin S0 is repeated. 4. For SEGRAM data, the lower 5 bits are used for display data. 5. If BE bit in the function set register is set to "1", the upper 1 bit (D7) in SEGRAM is used to control the blinking of the lower 5-bit pattern. When D7 is set to "1", the lower 5-bit display blinks. If bit D6 is "1", only the pattern of bit D4 can be blinked. 6. If SEGRAM data is "1", data is displayed; if "0", data isn't displayed.
30
LH1594/LH1595
8. CONFIGURATION OF DDRAM
Display positions vs. display data RAM (DDRAM) addresses
DIGIT COM0 to COM7 COM8 to COM15 1st 00 10 2nd 01 11 3rd 02 12 4th 03 13 5th 04 14 6th 05 15 7th 06 16 8th 07 17 9th 10th 11th 12th 13th 14th 15th 16th 08 09 0A 0B 0C 0D 0E 0F 18 19 1A 1B 1C 1D 1E 1F
The above addressing is used because 16 digits are displayed. The DDRAM stores data for 32 characters. Shift to right
If the display data is shifted, the DDRAM addresses are changed as follows :
DIGIT COM0 to COM7 COM8 to COM15 1st 1F 0F 2nd 00 10 3rd 01 11 4th 02 12 5th 03 13 6th 04 14 7th 05 15 8th 06 16 9th 10th 11th 12th 13th 14th 15th 16th 07 08 09 0A 0B 0C 0D 0E 17 18 19 1A 1B 1C 1D 1E
Shift to left
DIGIT COM0 to COM7 COM8 to COM15 1st 01 11 2nd 02 12 3rd 03 13 4th 04 14 5th 05 15 6th 06 16 7th 07 17 8th 08 18 9th 10th 11th 12th 13th 14th 15th 16th 09 0A 0B 0C 0D 0E 0F 10 19 1A 1B 1C 1D 1E 1F 00
NOTE :
* The memory in the DDRAM is configured as follows :
Display area (16 characters x 2 lines)
As shown above, the 2nd data appears following the end of the data in the 1st line. Notice that the addresses are consecutive.
31
LH1594/LH1595
9. DESCRIPTION OF SERIAL INTERFACE [FOR LH1594]
LH1594 is built in I2C BUS format interface. The I2C BUS is for bi-directional two-line communication between different ICs or modules.
9.1.1. DATA TRANSFER A change of SDA-state is allowed while SCL is low level. If SDA changes while SCL is high, this action is recognized as start bit or stop bit. 9.1.2. START SIGNAL When the bus is not busy, SDA transfers high to low while SCL is high. This state is defined as the start condition. 9.1.3. STOP SIGNAL When the bus is not busy, SDA transfers low to high while SCL is high. This state is defined as the stop condition.
9.1.
I2C
BUS Protocol
I2C BUS protocol consists of a data receiver and data transmitter. The device which controls protocol is the master, the device which is controlled is the slave. The master controls data transfer and provides clock signal. The LH1594 is used as a slave receiver or slave transmitter.
SCL SDA Start Signal Stop Signal
Start/Stop Timing
9.1.4. ACKNOWLEDGE Acknowledge bit is used to confirm data transfer. A transmitter (master or slave) releases the bus line after receiving 8-bit data. During next clock (9th
clock) receive, put low level on the bus to indicate data receive completely.
SCL SDA
1 Data
2 Data
8 Data
9
Acknowledge
Acknowledge Timing
32
LH1594/LH1595
9.1.5. DEVICE ADDRESS CODE After sending start bit, master device must transfer 8-bit device address code at first. Address code consists of 7 bits slave address and 1 bit R/W. During read operation, R/W bit is "1". During write operation, R/W bit is "0". 9.1.7. SECOND TRANSFERRED DATA During slave receive mode, LH1594 is specified as a control-byte waiting mode after receiving start condition and first cycle of 1 byte. Control-byte consists of 3 bits. These bits are used to specify function mode for operating instruction. Co
Slave address (7 bits) R/W ACK
{ "0" :: Slave receiver "1" Slave transmitter
Send Data at First Cycle
: This bit defines transfer mode. "0" : From next transfer byte, only data byte can be transferred. "1" : Next transfer byte is data byte and after next transfer byte, control-byte must be input again. : RS corresponds to "RS" signal in command function table. This bit identifies transfer data. : This bit defines read/write mode. "0" : Readable mode "1" : Write enable mode.
C0 RS R/W * * * * *
9.1.6. DEVICE ADDRESSING Bus master must generate start-condition to start data transfer between 2 devices. After generating start condition, master puts 8-bit word on SDA bus line. LH1594 is fixed higher order bits (corresponding to DB7 to DB2). To identify device, it is fixed to "011101". Next 1 bit is used to select LCD driver among some devices connecting to same bus. LH1594 can connect to same bus, up to 2 chips. SA0 is used for LSB bit for identifying device. 8th bit (R/W bit) defines operation mode. R/W = "0" : Write operation R/W = "1" : Read operation
0 1 1 1 0 1 SA0 R/W
RS
R/W
* mark means "Don't care". Transfer Data at Second Cycle
LH1594 Slave Address
33
LH1594/LH1595
9.2. Description of Pins Connected with The I2C BUS
SCL Serial clock input pin. SCL is used for clock of all data I/O. SDA SDA is bi-directional pin, which is used for data I/O. SDA is open drain pin, connect to VDD via pull-up resistor. SA0 SA0 is used for LSB bit of slave address (7 bits width). Must be fixed to "H" or "L" externally. ISEL ISEL selects whether to use I2C BUS or not. When ISEL is "H", I2C BUS is enable. If ISEL is low, I2C BUS operation of LH1594 is not warrantied.
34
LH1594/LH1595
9.3. Example of I2C BUS Operation
STEP I2C BUS TRANSFER BYTE 1 START I2C BUS Send slave address 2 SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK 0 3 1 1 1 0 1 0 0 1 ACK 0 0 0 0 0 1 Sets RE bit to "0". Send control byte C0 RS R/W 0 4 0 0 Control bits RS, C0 and R/W are specified. DISPLAY OPERATION Initialized. Nothing display. During the acknowledge cycle SDA will be pulled down by LH1594.
Set function D7 D6 D5 D4 D3 D2 D1 D0 ACK 0 0 1 0 0 0 0 0 1 Clear display D7 D6 D5 D4 D3 D2 D1 D0 ACK 000000 Control display ON/OFF 0 1 1
5
Display clear. Display and cursor are ON. All displays are cleared by operating display clear. Entry mode set. When writing into RAM, address is increased by 1 and cursor is shifted to right. Sets address to write into CGRAM.
6
D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 0000 Set entry mode 1 1 1 0 1
7
D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 000001101 Set CGRAM address D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 0 1 0 0 0 0 0 0 1 _ Send slave address Start condition
8
9
Sets RS bit to "1" and generated start condition again for writing.
10
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _ 01110 Send control byte 1 0 0 1 ACK _ 1 Writes data into CGRAM.
11
C0 RS R/W 0100 Write CGRAM data
0
0
0
0
12
D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 0 0 0 CG4 CG3 CG2 CG1 CG0 1 : : : Start condition
13
14
_
Generates start condition again for setting RS "0".
35
LH1594/LH1595
STEP 15 I2C BUS TRANSFER BYTE Send slave address SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _ 01110 Send control byte 16 C0 RS R/W 0 17 0 0 0 0 0 0 0 1 0 0 1 ACK _ 1 Sets address for writing into DDRAM. DISPLAY OPERATION
Set DDRAM address D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 1 0 0 0 0 0 0 0 1 _ Send slave address Start condition
18
Sets RS "1" and generates start condition again for writing into DDRAM.
19
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _ 01110 Send control byte 1 0 0 1 ACK _ 1 Writes "S".
20
C0 RS R/W 0100 Write DDRAM data
0
0
0
0
21
D7 D6 D5 D4 D3 D2 D1 D0 ACK S_ 010100111 : : : Write DDRAM data D7 D6 D5 D4 D3 D2 D1 D0 ACK SHARP_ 0101 Start condition 0 0 0 0 1 SHARP_ Send slave address
22
23
Writes "P".
24
Generates start condition again for setting RS "0".
25
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK SHARP_ 011101001 Send control byte C0 RS R/W 0 0 0 0 0 0 0 0 ACK SHARP_ 1 Sets DDRAM address so that cursor is positioned at the top of 2nd line.
26
27
Set DDRAM address SHARP D7 D6 D5 D4 D3 D2 D1 D0 ACK _ 100100001
36
LH1594/LH1595
STEP 28 I2C BUS TRANSFER BYTE Start condition DISPLAY SHARP _ Send slave address SHARP SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK _ 011101001 Send control byte C0 RS R/W 0 31 1 0 0 0 0 0 0 ACK 1 SHARP _ OPERATION Sets RS "1" and generates start condition again for writing into DDRAM.
29
30
Write DDRAM data SHARP D7 D6 D5 D4 D3 D2 D1 D0 ACK L_ 010011001 : : : Write DDRAM data
Writes "L".
32
33
34
SHARP D7 D6 D5 D4 D3 D2 D1 D0 ACK LCDDRIVER_ 010100101 Start condition SHARP LCDDRIVER_
Writes "R".
Generates start condition again for setting RS "0".
35
Send slave address SHARP SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK LCDDRIVER_ 011101001 Send control byte C0 RS R/W 10000 Set DDRAM address 0 0 0 ACK 1 SHARP LCDDRIVER_ Sets control bit C0 "1".
36
37
SHARP D7 D6 D5 D4 D3 D2 D1 D0 ACK LCDDRIVER_ 100000001 C0 RS R/W 0110 SHARP ACK LCDDRIVER_ 01 SHARP LCDDRIVER_
Sets address for reading out DDRAM data.
Send control byte 38 0 0 0
Sets control bit RS "1" and R/W "1".
Start condition 39
Generates start condition again for reading out DDRAM. Sets R/W "1" for reading out DDRAM data.
40
Send slave address SHARP SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W ACK LCDDRIVER_ 011101011
37
LH1594/LH1595
STEP 41 I2C BUS TRANSFER BYTE Read out data D7 D6 D5 D4 D3 D2 D1 D0 ACK MSB 42 : : : Read out data SHARP D7 D6 D5 D4 D3 D2 D1 D0 ACK LCDDRIVER_ MSB LSB 1 Stop condition 44 SHARP LCDDRIVER_ As master does not output acknowledge, data will not be output in the next cycle. LSB 0 DISPLAY SHARP LCDDRIVER_ OPERATION Reads out DDRAM data from MSB to LSB. Master outputs acknowledge.
43
Generates stop condition and finishes.
10. ABSOLUTE MAXIMUM RATINGS
Supply Supply Supply Supply Supply PARAMETER voltage (1) voltage (2) voltage (3) voltage (4) voltage (5) SYMBOL VDD VEE VOUT VR1, VR2 V0 V1, V2, V3, V4 VI TSTG APPLICABLE PINS VDD VEE VOUT VR1, VR2 V0 V1, V2, V3, V4 D7-D0, CSB, RS, M86, RDB, WRB, CK, CKS, OSCI, P/S, RESB, PMODE, SHL0, SHL1, TEST RATING -0.3 to +6.0 -0.3 to +6.0 -0.3 to +13.0 -0.3 to +13.0 -0.3 to +13.0 -0.3 to V0 + 0.3 UNIT V V V V V V NOTE
Supply voltage (6)
1, 2
Input voltage Storage temperature
-0.3 to VDD + 0.3 -45 to +125
V C
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to VSS (0 V).
11. RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage Operating voltage Operating temperature SYMBOL VDD VEE V0 VOUT VR1, VR2 TOPR APPLICABLE PINS VDD VEE V0 VOUT VR1, VR2 MIN. +2.2 +2.4 +4.0 +4.0 +4.0 -30 TYP. MAX. +5.5 +5.5 +11.0 +11.0 +11.0 +85 UNIT V V V V V C NOTE 1 2 3 4
NOTES :
1. The applicable voltage on any pin with respect to VSS (0 V). 2. When using the booster circuit, power supply, VEE at the primary circuit must be used within the above-described range. If the drive voltage of LCD panel can be boosted by utilizing the voltage level of VDD, usually connect this pin to VDD power supply. 3. Ensure that voltages are set such that VSS < V4 < V3 < V2 < V1 < V0. 4. The operating range is adjusted by the external circuit constructed between VOUT and VR1, VR2. The electric potential relation between the VR1, VR2 and VOUT pins must be VR2 VR1 VOUT.
38
LH1594/LH1595
12. ELECTRICAL CHARACTERISTICS 12.1. DC Characteristics
(Unless otherwise specified, VSS = 0 V, VDD = +2.2 to +5.5 V, TOPR = -30 to +85 C)
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current Output leakage current LCD drive output ON resistance Static LCD drive output ON resistance Standby current SYMBOL VIL VIH VOL VOH ILI ILO RON1 RON2 ISTB APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE D7-D0, CSB, RS, M86, RDB, 0 0.2VDD V WRB, CK, CKS, OSCI, P/S, VDD V RESB, PMODE, SHL0, SHL1 0.8VDD IOL = 0.4 mA 0.4 V D7-D0, LP, FLM, M IOH = -0.4 mA VDD - 0.4 V CSB, RS, M86, RDB, WRB, CK, CKS, OSCI, P/S, RESB, -10 VI = VSS or VDD 10 A PMODE, SHL0, SHL1 VI = VSS or VDD D7-D0, LP, FLM, M -10 10 A 1 |VON| SEG0-SEG79, COM0-COM15, V0 = 8 V 4 8 k$ 2 = 0.5 V COMI |VON| = 0.5 V SEGS0-SEGS9, COMS VDD VDD, VEE VDD, VEE OSCO 30 8.6 VOUT 5.7 RESB 10 s V 6 50 35 55 8 5 10 90 60 80 k$ A A A kHz 3 4 4 5 CONDITIONS
CK = 0 V VDD = 3 V CSB = VDD VDD = 5 V Boosting VDD = 3 V IDD1 Supply current (1) 3 times V0 = 6 V Boosting VDD = 3 V Supply current (2) IDD2 2 times V0 = 5 V RF = Oscillation frequency fOSC VDD = 3 V 1.2 M$2% Boosting VEE = 3 V 3 times Boosted output voltage VOUT Boosting VEE = 3 V 2 times Reset ("L") pulse width tRW
NOTES :
1. Applied when D7 to D0, LP, FLM, and M are in the high impedance state. 2. Resistance when 0.5 V is applied between each output pin and each power supply (V0, V1, V2, V3, V4 or VSS). Applied when power is supplied at power bias ratio of 1/7 in the external power supply mode. 3. Current at the VDD pin when the master clock stops, the chip is not selected (CSB = VDD), and no load is used. All circuits stop. 4. Applied when no access is made by the MPU when the internal oscillation circuit (RF = 1.2 M$) and power supply circuit (PMODE = "L") are used. The electronic volume is pre-set (the code is "1 1 1 1"). The display is fully lit-up (ALON = "1") and the LCD drive pin is not loaded. Measuring conditions : VDD = VEE, VR1 = VR2, C1 = C2 = 1 F, R1 + R2 + R3 = 4 M$, the current flowing through voltage control resistors (R1, R2, and R3) is included. 5. Oscillation frequency when connecting a feedback resistor (RF) of 1.2 M$ between OSCI and OSCO. 6. Applied when the internal oscillation circuit (RF = 1.2 M$) and power supply circuit (PMODE = "L") are used. Measuring conditions : C1 = C2 = 1 F, VOUT pin is connected only to C1 and the LCD drive pin is not loaded.
39
LH1594/LH1595
12.2. AC Characteristics
12.2.1. SYSTEM BUS READ/WRITE TIMING (80-FAMILY MPU) (Write Timing)
tAS8 CSB RS tAH8
tWRW8 WRB tDS8 D7-D0 tCYC8 tDH8
(Read Timing)
tAS8 CSB RS tAH8
tRDW8 RDB tRDH8 D7-D0 tRDD8 tCYC8
40
LH1594/LH1595
(80-family MPU Timing Characteristics)
PARAMETER Address hold time Address setup time System cycle time Read pulse width Write pulse width Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS
(VDD = 4.5 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS CSB RS WRB RDB D7-D0 D7-D0 All of above pins MIN. 60 20 400 200 50 50 20 150 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.7 to 4.5 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Read pulse width Write pulse width Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS APPLICABLE PINS CSB RS WRB RDB D7-D0 D7-D0 All of above pins MIN. 100 40 600 400 100 100 40 300 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.2 to 2.7 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Read pulse width Write pulse width Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH8 tAS8 tCYC8 tRDW8 tWRW8 tDS8 tDH8 tRDD8 tRDH8 tR, tF CL = 15 pF CONDITIONS APPLICABLE PINS CSB RS WRB RDB D7-D0 D7-D0 All of above pins MIN. 200 80 1 200 600 150 150 80 500 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
41
LH1594/LH1595
12.2.2. SYSTEM BUS READ/WRITE TIMING (68-FAMILY MPU) (Write Timing)
tCYC6 E tEW6 tAS6
R/W
CSB RS tDS6 D7-D0 tDH6 tAH6
(Read Timing)
tCYC6 E tEW6
R/W
tAS6 tAH6
CSB RS
D7-D0 tRDD6 tRDH6
42
LH1594/LH1595
(68-family MPU Timing Characteristics)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS
(VDD = 4.5 to 5.5 V, TOPR = -30 to +85 C)
APPLICABLE PINS CSB RS MIN. 60 20 400 200 50 D7-D0 D7-D0 All of above pins 50 20 150 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.7 to 4.5 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS APPLICABLE PINS CSB RS MIN. 100 40 600 400 100 D7-D0 D7-D0 All of above pins 100 40 300 10 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
(VDD = 2.2 to 2.7 V, TOPR = -30 to +85 C)
PARAMETER Address hold time Address setup time System cycle time Enable pulse width (READ) Enable pulse width (WRITE) Data setup time Data hold time Read data output delay time Read data hold time Input signal rise and fall time SYMBOL tAH6 tAS6 tCYC6 tEW6 tDS6 tDH6 tRDD6 tRDH6 tR, tF CL = 15 pF E CONDITIONS APPLICABLE PINS CSB RS MIN. 200 80 1 200 600 150 150 80 500 10 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
D7-D0 D7-D0 All of above pins
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
43
LH1594/LH1595
12.2.3. SERIAL INTERFACE TIMING (I2C BUS) [FOR LH1594]
SDA tBUF tLOW tR tHD:DAT tSU:DAT tSU:STA
SCL tHD:STA tHIGH fSCL tF tSU:STO
(VDD = 2.2 to 5.5 V, TOPR = -30 to +85 C)
PARAMETER SCL clock frequency Start condition hold time SCL LOW time SCL HIGH time Bus free time Data setup time Data hold time Setup time for START condition Setup time for STOP condition SCL and SDA rise time SCL and SDA fall time SYMBOL fSCL tHD:STA tLOW tHIGH tBUF tSU:DAT tHD:DAT tSU:STA tSU:STO tR tF SCL SDA SDA CONDITIONS APPLICABLE PINS MIN. 4.7 4.7 4 4.7 250 0 4.7 4 1 0.3 MAX. 100 UNIT kHz s s s s ns ns s s s s
SCL
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
44
LH1594/LH1595
12.2.4. SERIAL INTERFACE TIMING [FOR LH1595]
tCSS CSB tCSH
RS tASS tSLW SCL tDSS SDA tCYCS tAHS
tSHW tDHS
(VDD = 4.5 to 5.5 V, TOPR = -30 to +85 C)
PARAMETER Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB to SCL time CSB hold time Input signal rise and fall time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH tR, tF CONDITIONS APPLICABLE PINS SCL MIN. 500 200 200 40 40 200 200 40 40 15 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
RS SDA CSB All of above pins
(VDD = 2.2 to 4.5 V, TOPR = -30 to +85 C)
PARAMETER Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CSB to SCL time CSB hold time Input signal rise and fall time SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH tR, tF CONDITIONS APPLICABLE PINS SCL MIN. 1 000 400 400 RS SDA CSB All of above pins 80 80 400 400 80 80 30 MAX. UNIT ns ns ns ns ns ns ns ns ns ns
NOTE : All the timings must be specified relative to 20% and 80% of VDD voltage.
45
LH1594/LH1595
13. CONNECTION EXAMPLES OF REPRESENTATIVE APPLICATIONS
(a) Connection to The 80-family MPU
2.2 to 5.5 V VCC A0 A7-A1 AE (80-family MPU) D7-D0 GND Reset input 7 Decoder RS CSB D7-D0 RDB WRB RESB VSS (LH1594/LH1595) VDD
8
(b) Connection to The 68-family MPU
2.2 to 5.5 V VCC A0 A15-A1 VMA (68-family MPU) D7-D0 E R/ GND Reset input 15 Decoder RS CSB D7-D0 RDB (E) WRB (R/W) RESB VSS (LH1594/LH1595) VDD
8
46
LH1594/LH1595
(c) Connection to The MPU with Serial Interface
2.2 to 5.5 V VCC A0 A7-A1 (MPU) PORT1 PORT2 GND Reset input SDA SCL RESB VSS 7 Decoder RS CSB (LH1594/LH1595) VDD
* When connecting multiple LH1594/LH1595s, input to each CSB pin by varying the decoder conditions of address signals.
47
LH1594F
Film center Device center 1.1MAX. Total 0.75MAX. Backside 34.975 31.82 12.50.5 Pattern side 25.4 (SL) 0.2MAX.
14. PACKAGE
V0 V1 V2 V3 V4 VSS SHL0 VDD SHL1 VSS TEST RESB CSB RS M86 P/S WRB RDB PMODE CK CKS OSCI OSCO LP FLM M D0 D1 D2 D3 D4/ISEL D5/SA0 D6/SCL D7/SDA VDD VEE CAP1- CAP1+ CAP2- CAP2+ VOUT VR1 VR2 P0.55 x (43 - 1) = 23.10.03 W0.2750.02 5.1 (SL) [0.5] 0.6 (SL) 9.85 (SL) 5.525 7.9 (SL) 5.525
O2.0 (Good device hole)
2.0 (SL)
7.8
8.80.5
UPILEX is a trademark of UBE INDUSTRIES, LTD..
20.00.05 (Holes) O1.8 (SR) 0.2 O1.2 (Hole) 2-R0.6 (Hole) 2.7 (SL) Sprocket center 3.65 (SR) 3.95 5.4MAX. (Resin area) Chip center 4.75 2-R0.9 (SR) 13.2MAX. (Resin area) 1.42
[6.45 (Cut line)]
[13.5 (Cut line)]
48
4.05 (SR) P0.22 x (112 - 1) = 24.420.03 W0.11 25.40.035 1.0(SL) 12.9 [26.8 (Cut line)] COM6 COM7 DUMMY 12.9 [3.0TYP.(2.7MIN.)] SEG1 SEG0 SEGS0 SEGS1 SEGS2 SEGS3 SEGS4 COMS COMI COM0 COM1 COM9 COM8 COMS SEGS9 SEGS8 SEGS7 SEGS6 SEGS5 SEG79 SEG78
2.7 (SL)
5.850.05
[7.05 (Cut line)]
1.42
1.0(SL)
[0.5]
DUMMY COMI COM15 COM14
PACKAGES FOR LCD DRIVERS
0.60.02
0.40.02
o Tape Specification
Tape width Tape type Perforation pitch 35 mm Super wide 4 pitches
o Tape Material
Substrate Adhesive Cu foil [thickness] Solder resist UPILEX S75 #7100 VLP 25 m Epoxy resin (Unit : mm)
0.40.02
0.60.02

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